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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad15700 1 msps 16-/14-bit analog i/o port features 16-bit a/d converter 1 msps s/(n + d): 90 db typ @ 250 khz no pipeline delay 14-bit d/a converter settling time: 1 s s/n: 92 db typ 2 80 mhz amplifiers 30 v/ s slew rate rail-to-rail input and output output current 15 ma 2 gain setting center tapped resistors resistor ratio tracking: 2 ppm/ c unipolar operation spi /qspi/microwire/dsp compatible 132 mw typical power dissipation applications optical mems mirror control industrial process control data acquisition instrumentation communication product highlights 1. fast throughput adc. the ad15700 incorporates a high speed, 1 msps, 16-bit sar adc. 2. superior adc inl. the 16-bit adc has a maximum integral nonlineariy of 2.5 lsb with no missing codes. 3. two precision resistor networks with 2 ppm/ c ratio tracking for gain setting. 4. low power consumption. typically 132 mw at maximum performance levels. 5. industrial temperature range: ?0 c to +85 c. general description the ad15700 is a precision component to interface analog input and output channels to a digital processor. it is ideal for area- limited applications that require maximum circuit density. the ad15700 contains the functionality of a 16-bit, 1 msps charge redistribution sar analog-to-digital converter that operates from a 5 v power supply. the high speed 16-bit sampling adc incor- porates a resistor input scaler that allows various input ranges, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. the ad15700 also contains a 14-bit, serial input, voltage output dac that operates from a 5 v supply and has a settling time of 1 m s. two single- or split-supply voltage feedback amplifiers with rail-to-rail input and output characteristics featuring 80 mhz of small signal bandwidth and 10 m v/ c offset drift provide adc and dac buffering capability. the center tapped 3 k w resistors are precision resistor networks with 2 ppm/ c ratio tracking that provide low gain drift when used for scaling. the adc, dac, and amp functions are electrically isolated from each other to provide maximum design flexibility. input and output signal conditioning circuits for the converters can be easily configured with short interconnects under the device at the board level. the ad15700 is available in a 10 mm cspbga package. functional block diagram serial port p arallel interface 16 r 2r 4r 4r sar adc control logic and calibration circuitry clock switched cap dac ovdd ognd ser/ par busy d[15:0] cs_adc rd ob/ 2c byteswap w arp impulse cnvst av d d ag nd_adc ref refgnd dvdd dgnd adc ind(4r) inc(4r) inb(2r) ina(r) ingnd pd reset serial input register 14-bit data latch control logic 14-bit dac vdd_dac dgnd_dac cs_dac din sclk vref vout _ dac ag nd_dac ?s2 + vs2 ?s1 + vs1 ad15700 ra1 rb1 rc1 rb2 rc2 ra2 + in2 ?n2 vout2 ?n1 + in1 vout1 rpad2 rpad1 common 1.5k 1.5k 1.5k 1.5k
rev. a ? ad15700?pecifications parameter condition min typ max unit resolution 16 bits analog input voltage range vind ?vingnd 4 ref, 0 v to 4 ref, 2 ref (see table i) common-mode input voltage vingnd ?.1 +0.5 v analog input cmrr f in = 100 khz 74 db input impedance see table i throughput speed complete cycle in warp mode 1 m s throughput rate in warp mode 1 1000 ksps time between conversions in warp mode 1 ms complete cycle in normal mode 1.25 m s throughput rate in normal mode 0 800 ksps complete cycle in impulse mode 1.5 m s throughput rate in impulse mode 0 666 ksps dc accuracy integral linearity error ?.5 +2.5 lsb 1 no missing codes 16 bits transition noise 0.7 lsb bipolar zero error 2 , t min to t max 5 v range, normal or ?5 +45 lsb impulse modes other range or mode 0.1% % of fsr bipolar full-scale error 2 , t min to t max ?.38 +0.38 % of fsr unipolar zero error 2 , t min to t max ?.18 +0.18 % of fsr unipolar full-scale error 2 , t min to t max ?.76 +0.76 % of fsr power supply sensitivity avdd = 5 v 5% 9.5 lsb ac accuracy signal-to-noise f in = 20 khz 89 90 db 3 f in = 250 khz 90 db spurious-free dynamic range f in = 250 khz 100 db total harmonic distortion f in = 20 khz ?00 ?6 db f in = 250 khz ?00 db signal-to-(noise + distortion) f in = 20 khz 88.5 90 db f in = 250 khz, ?0 db input 30 db ? db input bandwidth 9.6 mhz sampling dynamics aperture delay 2ns aperture jitter 5 ps rms transient response full-scale step 250 ns reference external reference voltage range 2.3 2.5 3.0 v external reference current drain 1 msps throughput 200 m a digital inputs logic levels v il ?.3 +0.8 v v ih +2.0 dvdd + 0.3 v i il ? +1 m a i ih ? +1 m a 16-bit adc electrical characteristics (?0 c to +85 c, avdd = dvdd = 5 v, 0vdd = 2.7 v to 5.25 v, unless otherwise noted.)
rev. a ad15700 ? parameter condition min typ max unit digital outputs data format parallel or serial 16-bit pipeline delay conversion results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = ?70 m a ovdd ?0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v operating current 4 avdd 15 ma dvdd 5 7.2 ma ovdd 5 37 m a power dissipation 5, 6 666 ksps throughput 7 84 95 mw 100 sps throughput 7 15 m w 1 msps throughput 4 112 125 mw in power-down mode 8 1mw temperature range specified performance t min to t max ?0 +85 c notes 1 lsb means least significant bit. with the 5 v input range, one lsb is 152.588 m v. 2 these specifications do not include the error contribution from the external reference. 3 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full scale, unless otherwise specified. 4 in warp mode. 5 tested in parallel reading mode. 6 tested with the 0 v to 5 v range and vin ?vingnd = 0 v. 7 in impulse mode. 8 with ovdd below dvdd + 0.3 v and all digital inputs forced to ovdd or ognd, respectively. specifications subject to change without notice. table i. analog input configuration input voltage range ind(4r) inc(4r) inb(2r) ina(r) input impedance 1 4 ref v in ingnd ingnd ref 1.63 k w 2 ref v in v in ingnd ref 948 w ref v in v in v in ref 711 w 0 v to 4 ref v in v in ingnd ingnd 948 w 0 v to 2 ref v in v in v in ingnd 711 w 0 v to ref v in v in v in v in note 2 notes 1 typical analog input impedance. 2 for this range, the input is high impedance.
rev. a ? ad15700 16-bit adc timing characteristics (?0 c to +85 c, avdd = dvdd = 5 v, 0vdd = 2.7 v to 5.25 v, unless otherwise noted.) parameter symbol min typ max unit refer to figures 14 and 15 convert pulsewidth t 1 5ns time between conversions t 2 1/1.25/1.5 note 1 m s (warp mode/normal mode/impulse mode) cnvst low to busy high delay t 3 30 ns busy high all modes except in master serial read after t 4 0.75/1/1.25 m s convert mode (warp mode/normal mode/impulse mode) aperture delay t 5 2ns end of conversion to busy low delay t 6 10 ns conversion time (warp mode/normal mode/impulse mode) t 7 0.75/1/1.25 m s acquisition time t 8 1 m s reset pulsewidth t 9 10 ns refer to figures 16, 17, and 18 (parallel interface modes) cnvst low to data valid delay t 10 0.75/1/1.25 m s (warp mode/normal mode/impulse mode) data valid to busy low delay t 11 20 ns bus access request to data valid t 12 40 ns bus relinquish time t 13 515ns refer to figures 20 and 21 (master serial interface modes) 2 cs_adc low to sync valid delay t 14 10 ns cs_adc low to internal sclk valid delay t 15 10 ns cs_adc low to sdout delay t 16 10 ns cnvst low to sync delay (read during convert) t 17 25/275/525 ns (warp mode/normal mode/impulse mode) sync asserted to sclk first edge delay 3 t 18 4ns internal sclk period 3 t 19 25 40 ns internal sclk high 3 t 20 15 ns internal sclk low 3 t 21 9ns sdout valid setup time 3 t 22 4.5 ns sdout valid hold time 3 t 23 2ns sclk last edge to sync delay 3 t 24 3ns cs_adc high to sync hi-z t 25 10 ns cs_adc high to internal sclk hi-z t 26 10 ns cs_adc high to sdout hi-z t 27 10 ns busy high in master serial read after convert 3 t 28 see table ii m s cnvst low to sync asserted delay t 29 0.75/1/1.25 m s master serial read after convert sync deasserted to busy low delay t 30 25 ns refer to figures 22 and 24 (slave serial interface modes) external sclk setup time t 31 5ns external sclk active edge to sdout delay t 32 316ns sdin setup time t 33 5ns sdin hold time t 34 5ns external sclk period t 35 25 ns external sclk high t 36 10 ns external sclk low t 37 10 ns notes 1 in warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2 in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 3 in serial master read during convert mode. see table ii. specifications subject to change without notice.
rev. a ad15700 ? 1.6ma i ol i oh 500ma c l 60pf to output pin in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise the load is 60pf maximum. 1.4v figure 1. load circuit for digital interface timing, sdout, sync, sclk outputs, c l = 10 pf 0.8v t delay 2v t delay 0.8v 2v 2v 0.8v figure 2. voltage reference levels for timing table ii. serial clock timings in master read after convert divsclk[1] 0011 divsclk[0] symbol 0101unit sync to sclk first edge delay minimum t 18 4202 020ns internal sclk period minimum t 19 25 50 100 200 ns internal sclk period maximum t 19 40 70 140 280 ns internal sclk high minimum t 20 15 25 50 100 ns internal sclk low minimum t 21 9244 999ns sdout valid setup time minimum t 22 4.5 22 22 22 ns sdout valid hold time minimum t 23 24308 9ns sclk last edge to sync delay minimum t 24 360 140 300 ns busy high width maximum (warp) t 28 1.5 2 3 5.25 m s busy high width maximum (normal) t 28 1.75 2.25 3.25 5.5 m s busy high width maximum (impulse) t 28 2 2.5 3.5 5.75 m s
rev. a ? ad15700 14-bit dac electrical characteristics (t a = ?0 c to +85 c, v dd _dac = 5 v, v ref = 2.5 v, unless otherwise noted.) parameter condition min typ max unit static performance resolution 1 lsb = v ref /2 14 = 153 m v when v ref = 2.5 v 14 bits relative accuracy, inl 0.15 1.0 lsb differential nonlinearity guaranteed monotonic 0.15 0.8 lsb gain error ?.75 ?.3 0 lsb gain error temperature coefficient 0.1 ppm/ c zero code error 0 0.1 0.5 lsb zero code temperature coefficient 0.05 ppm/ c output characteristics output voltage range 0 v ref ? lsb v output voltage settling time to 1/2 lsb of fs, c l = 10 pf 1 m s digital-to-analog glitch impulse 1 lsb change around the major carry 10 nv? digital feedthrough all 1s loaded to dac, v ref = 2.5 v 0.05 nv? dac output impedance tolerance typically 20% 6.25 k w power supply rejection ratio d v dd 10% 1.0 lsb dac reference input reference input range 2 v dd v reference input resistance * 9k w logic inputs input current 1.0 m a vinl, input low voltage 0.8 v vinh, input high voltage 2.4 v input capacitance 10 pf hysteresis voltage 0.4 v reference reference ? db bandwidth all 1s loaded 1.3 mhz reference feedthrough all 0s loaded, v ref = 1 v p-p at 100 khz 1 mv p-p signal-to-noise ratio 92 db reference input capacitance code 0000 h 75 pf code 3fff h 120 pf power requirements v dd 4.5 5.50 v i dd 0.3 1.1 ma power dissipation 1.5 6.05 mw * reference input resistance is code-dependent, minimum at 2555 h . specifications subject to change without notice.
rev. a ad15700 ? 14-bit dac timing characteristics 1, 2 (v dd = 5 v, 5%, v ref = 2.5 v, agnd = dgnd = 0 v. all specifications t a = t min to t max , unless otherwise noted). parameter limit at t min , t max all versions unit description f sclk 25 mhz max sclk cycle frequency t 1 40 ns min sclk cycle time t 2 20 ns min sclk high time t 3 20 ns min sclk low time t 4 15 ns min cs_dac low to sclk high setup t 5 15 ns min cs_dac high to sclk high setup t 6 35 ns min sclk high to cs_dac low hold time t 7 20 ns min sclk high to cs_dac high hold time t 8 15 ns min data setup time t 9 0 ns min data hold time t 10 30 ns min cs_dac high time between active periods notes 1 guaranteed by design. not production tested. 2 sample tested during initial release and after any redesign or process change that may affect this parameter. all input signals are measured with tr = tf = 5 ns (10% to 90% of 3 v and timed from a voltage level of 1.6 v). specifications subject to change without notice. t 2 t 3 t 7 t 5 t 8 t 9 t 1 t 6 t 4 t 10 db13 db0 din cs_dac sclk figure 3. timing diagram
rev. a ? ad15700 amplifier electrical characteristics [5 v supply (t a = 25 c, v s = 5 v, r l = 1 k to 2.5 v, r f = 2.5 k , unless otherwise noted.)] parameter condition min typ max unit dynamic performance ? db small signal bandwidth g = +1, v o < 0.4 v p-p 54 80 mhz slew rate g = ?, v o = 2 v step 27 32 v/ m s settling time to 0.1% g = ?, v o = 2 v step, c l = 10 pf 125 ns distortion/noise performance total harmonic distortion f c = 1 mhz, v o = 2 v p-p, g = +2 ?2 dbc f c = 100 khz, v o = 2 v p-p, g = +2 ?6 dbc input voltage noise f = 1 khz 15 nv/ hz input current noise f = 100 khz 2.4 pa / hz f = 1 khz 5 pa / hz differential gain r l = 1 k w 0.17 % differential phase r l = 1 k w 0.11 degrees dc performance input offset voltage v cm = v cc /2; v out = 2.5 v 1 6mv t min to t max 6 10 mv offset drift v cm = v cc /2; v out = 2.5 v 5 m v/ c input bias current v cm = v cc /2; v out = 2.5 v 0.45 1.2 m a t min to t max 2.0 m a input offset current 50 350 na open-loop gain v cm = v cc /2; v out = 1.5 v to 3.5 v 76 82 db t min to t max 74 db input characteristics common-mode input resistance 40 m w differential input resistance 280 k w input capacitance 1.6 pf input voltage range ?.5 to +5.5 v input common-mode voltage range ?.2 to +5.2 v common-mode rejection ratio v cm = 0 v to 5 v 56 70 db v cm = 0 v to 3.8 v 66 80 db differential/input voltage 3.4 v output characteristics output voltage swing low r l = 10 k w 0.05 0.02 v output voltage swing high 4.95 4.98 v output voltage swing low r l = 1 k w 0.2 0.1 v output voltage swing high 4.8 4.9 v output current 15 ma short circuit current sourcing 28 ma sinking ?6 ma capacitive load drive g = +2 15 pf power supply operating range 2.7 12 v quiescent current per amplifier 800 1400 m a power supply rejection ratio v s ?= 0 v to ? v or 75 86 db v s + = 5 v to 6 v operating temperature range ?0 +85 c specifications subject to change without notice.
rev. a ad15700 ? amplifier electrical characteristics [ 5 v supply (t a = 25 c, v s = 5 v, r l = 1 k to 0 v, r f = 2.5 k , unless otherwise noted.)] parameter condition min typ max unit dynamic performance ? db small signal bandwidth g = +1, v o < 0.4 v p-p 54 80 mhz slew rate g = ?, v o = 2 v step 30 35 v/ m s settling time to 0.1% g = ?, v o = 2 v step, c l = 10 pf 125 ns distortion/noise performance total harmonic distortion f c = 1 mhz, v o = 2 v p-p, g = +2 ?2 dbc f c = 100 khz, v o = 2 v p-p, g = +2 ?6 dbc input voltage noise f = 1 khz 15 nv / hz input current noise f = 100 khz 2.4 pa / hz f = 1 khz 5 pa / hz differential gain r l = 1 k w 0.15 % differential phase r l = 1 k w 0.15 degrees dc performance input offset voltage v cm = 0 v; v out = 0 v 1 6 mv t min to t max 6 10 mv offset drift v cm = 0 v; v out = 0 v 5 m v/ c input bias current v cm = 0 v; v out = 0 v 0.45 1.2 m a t min to t max 2.0 m a input offset current 50 350 na open-loop gain v cm = 0 v; v out = 2 v 76 80 db t min to t max 74 db input characteristics common-mode input resistance 40 m w differential input resistance 280 k w input capacitance 1.6 pf input voltage range ?.5 to +5.5 v input common-mode voltage range ?.2 to +5.2 v common-mode rejection ratio v cm = ? v to +5 v 60 80 db v cm = ? v to +3.5 v 66 90 db differential/input voltage 3.4 v output characteristics output voltage swing low r l = 10 k w ?.94 ?.98 v output voltage swing high +4.94 +4.98 v output voltage swing low r l = 1 k w ?.7 ?.85 v output voltage swing high +4.7 +4.75 v output current 15 ma short circuit current sourcing +35 ma sinking ?0 ma capacitive load drive g = +2 15 pf power supply operating range 1.35 6 v quiescent current per amplifier 900 1600 m a power supply rejection ratio v s ?= ? v to ? v or 76 86 db v s + = +5 v to +6 v operating temperature range ?0 +85 c specifications subject to change without notice.
rev. a ?0 ad15700 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad15700 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * analog inputs ind, inc, inb . . . . . . . . . . . . . . . . . . . . . . ?1 v to +30 v ina, ref, ingnd, refgnd, agnd . . . ?.3 v to avdd + 0.3 v adc ground voltage differences agnd_adc, dgnd_adc, ognd . . . . . . . . . . . . 0.3 v adc supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v adc digital inputs . . . . . . . . . . . . . ?.3 v to dvdd + 0.3 v vdd_dac to agnd_dac . . . . . . . . . . . . . . . ?.3 v to +6 v dac digital input voltage to dgnd_dac . . . . . . . . . . . . . . . . ?.3 v to dvdd + 0.3 v vout_dac to agnd_dac . . . . ?.3 v to dvdd + 0.3 v agnd_dac to dgnd_dac . . . . . . . . . . . ?.3 v to +0.3 v dac input current to any dac pin except supplies . . 10 ma resistor divider electrical characteristics (@ t a = 25 c, unless otherwise noted.) parameter condition min typ max unit resistance 2.97 3.00 3.03 k w temperature coefficient of resistance 50 ppm/ c resistance ratio of two halves 0.99 1.0 1.01 resistance ratio tracking 2 ppm/ c power dissipation t a = 70 c 250 * mw * at higher temperatures, linearly derates to 0 mw at 175 c. specifications subject to change without notice. amplifier supply voltage (vs1, vs2) . . . . . . . . . . . . . . 12.6 v amplifier input voltage (common mode) . . . . . . v s 0.5 v amplifier differential input voltage . . . . . . . . . . . . . . . 3.4 v amplifier output short circuit duration . . . . . . . . . . . . . . observe power derating curves resistor instantaneous voltage drop . . . . . . . . . . . . . . . 50 v internal power dissipation . . . . . . . . . . . . . (t j m ax ?t a )/ ja thermal resistance ja 10 mm cspbga . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 c/w maximum junction temperature (t j m ax) . . . . . . . . . . 150 c operating temperature range . . . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . . . ?5 c to +150 c lead temperature . . . . . . . . . . . . . . . . . . . . . . . 225 c, 15 sec * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide model temperature range package option ad15700bca ?0 c to +85 c 144-lead cspbga ad15700/pcb 25 c evaluation board adds-2191-ezlite 25 c evaluation kit * adds-21535-ezlite adds-21160m-ezlite adds-21161n-ezlite * one of the dsp evaluation kits is required for operation of the ad15700/pcb evaluation board.
rev. a ad15700 ?1 adc pin function descriptions (see pinout, page 42) pin no. mnemonic type description h9, j8, agnd_adc p analog power ground pin j9, m12 m6 avdd p input analog power pin. nominally 5 v. l7 byteswap di parallel mode selection (8-/16-bit). when low, the lsb is output on d[7:0] and the msb is output on d[15:8]. when high, the lsb is output on d[15:8] and the msb is output on d[7:0]. l8 ob/ 2c di straight binary/binary twos complement. when ob/ 2c is high, the digital output is straight binary; when low, the msb is inverted, resulting in a twos complement output from its internal shift register. m7 warp di mode selection. when high and impulse low, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. when low, full accuracy is maintained independent of the minimum conversion rate. l9 impulse di mode selection. when high and warp low, this input selects a reduced power mode. in this mode, the power dissipation is approximately proportional to the sampling rate. m8 ser/ par di serial/parallel selection input. when low, the parallel port is selected; when high, the serial interface mode is selected and some bits of the data bus are used as a serial port. m9, l10 d[0:1] do bit 0 and bit 1 of the parallel port data output bus. when ser/ par is high, these outputs are in high impedance. m10, l11 d[2:3] or di/o when ser/ par is high, ext/ int is low and rdc/sdin is low, which is the divsclk[0:1] serial master read divsclk[0:1] after convert mode. these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. in the other serial modes, these inputs are not used. m11 d[4] or ext/ int di/o when ser/ par is low, this output is used as bit 4 of the parallel port data output bus. when ser/ par is high, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock, called, respectively, master and slave mode. with ext/ int tied low, the internal clock is selected on sclk output. with ext/ int set to a logic high, output data is synchronized to an external clock signal connected to the sclk input and the external clock is gated by cs_adc . l12 d[5] or invsync di/o when ser/ par is low, this output is used as bit 5 of the parallel port data output bus. when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal. when low, sync is active high. when high, sync is active low. k11 d[6] or invsclk di/o when ser/ par is low, this output is used as bit 6 of the parallel port data output bus. when ser/ par is high, this input, part of the serial port, is used to invert the sclk signal. it is active in both master and slave mode. k12 d[7] or rdc/sdin di/o when ser/ par is low, this output is used as bit 7 of the parallel port data output bus. when ser/ par is high, this input, part of the serial port, is used as either an external data input or a read mode selection input, depending on the state of ext/ int . when ext/ int is high, rdc/sdin could be used as a data input to daisy-chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on data with a delay of 16 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the previous data is output on sdout during conversion. when rdc/sdin is low, the data can be output on sdout only when the conversion is complete. j10 ognd p input/output interface digital power ground j11 ovdd p input/output interface digital power. nominally at the same supply as the supply of the host interface (5 v or 3.3 v). j12 dvdd p digital power. nominally at 5 v.
rev. a ?2 ad15700 adc pin function descriptions (continued) pin no. mnemonic type description h10 dgnd_adc p digital power ground h12 d[8] or sdout do when ser/ par is low, this output is used as bit 8 of the parallel port data output bus. when ser/ par is high, this input, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in an on-chip register. the adc provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/ 2c . in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated on sclk rising edge and valid on the next falling edge. if invsclk is high, sdout is updated on sclk falling edge and valid on the next rising edge. h11 d[9] or sclk di/o when ser/ par is low, this output is used as bit 9 of the parallel port data output bus. when ser/ par is high, this input, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. g12 d[10] or sync do when ser/ par is low, this output is used as bit 10 of the parallel port data output bus. when ser/ par is high, this input, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sync is driven high and remains high while sdout output is valid. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. g11 d[11] or rderror do when ser/ par is low, this output is used as bit 11 of the parallel port data output bus. when ser/ par is high and ext/ int is high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and rderror is pulsed high. f12, f11, d[12:15] do b it 12 to bit 15 of the parallel port data output bus. when ser/ par is high, e12, e11 these outputs are in high impedance. g10 busy do busy output. transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. the falling edge of busy could be used as a data ready clock signal. g9 dgnd_adc p must be tied to digital ground e10 rd di read data. when cs_adc and rd are both low, the interface parallel or serial output bus is enabled. k10 cs_adc di chip select. when cs_adc and rd are both low, the interface parallel or serial output bus is enabled. cs_adc is also used to gate the external serial clock. d12 reset di reset input. when set to a logic high, reset the adc. current conversion, if any, is aborted. if not used, this pin could be tied to dgnd. k9 pd di power-down input. when set to a logic high, power consumption is reduced and conversions are inhibited after the current one is completed. e7 cnvst di start conversion. a falling edge on cnvst puts the internal sample/hold into the hold state and initiates a conversion. in impulse mode (impulse high and warp low), if cnvst is held low when the acquisition phase (t 8 ) is complete, the internal sa mpl e/hold is put into the hold state and a conversion is immediately started. h8 agnd_adc p must be tied to analog ground g5 ref ai reference input voltage h5 refgnd ai reference input analog ground j7 ingnd p analog input ground j5, k5, ina, inb, ai analog inputs. refer to table i for input range configuration. l5, m5 inc, ind
rev. a ad15700 ?3 dac pin function descriptions pin no. mnemonic type description a6 vout_dac ao analog output voltage from the dac a3, c3, c4 agnd_dac p ground reference point for analog circuitry a2 vref ai this is the voltage reference input for the dac. connect to external reference ranges from 2 v to vdd. b1 cs_dac di this is an active low logic input signal. the chip select signal is used to frame the serial data input. e1 sclk di clock input. data is clocked into the input register on the rising edge of sclk. duty cycle must be between 40% and 60%. e2 din di serial data input. this device accepts 14-bit words. data is clocked into the input register on the rising edge of sclk. e3 dgnd_dac p digital ground. ground reference for digital circuitry. c6 vdd_dac p analog supply voltage, 5 v 10% amplifier pin function descriptions pin no. mnemonic type description c9 (j1) +in1(2) ai positive input voltage a9 (g1) ?n1(2) ai negative input voltage b12 (k4) vout1(2) ao amplifier output voltage a11 (f3) +vs1(2) p analog positive supply voltage b10, b11 ?s1(2) p analog negative supply voltage (g3, h3) resistor pin function descriptions pin no. mnemonic type description b9 (l4) ra1(2) ai/o resistor end terminal a8 (m4) rb1(2) ai/o resistor center tap d9 (l1) rc1(2) ai/o resistor end terminal a7 (m3) rpad1(2) p resistor die pad. tie to analog ground. common pin function descriptions pin no. mnemonic type description a1, a4, a5, a10, a12, b2?8, c1, common p common floating net connecting 69 pins. not electrically c2, c5, c7, c8, c10?12, d1?8, connected within the module. tie at least one of these pins d10, d11, e4?6, e8, e9, f1, f2, to analog ground. f4?10, g2, g4, g6?8, h1, h2, h4, h6, h7, j2?4, j6, k1?3, k6?8, l2, l3, l6, m1, m2 notes ai = analog input ai/o = bidirectional analog ao = analog output di = digital input di/o = bidirectional digital do = digital output p = power
rev. a ?4 ad15700 adc definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from ?egative full scale?through ?ositive full scale.?the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 011...10 to 011...11 in twos comple- ment coding) should occur for an analog voltage 1 1/2 lsb below the nominal full scale (2.499886 v for the 2.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. bipolar zero error the difference between the ideal midscale input voltage (0 v) and the actual voltage producing the midscale output code. unipolar zero error in unipolar mode, the first transition should occur at a level 1/2 lsb above analog ground. the unipolar zero error is the deviation of the actual transition from that point. spurious free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) a measurement of the resolution with a sine wave input. it is related to s/(n + d) by the following formula: enob s n d db =+ [] () () /./. 176 602 and is expressed in bits. total harmonic distortion (thd) the rms sum of the first five harmonic components to the rms value of a full-scale input signal; expressed in decibels. signal-to-noise ratio (snr) the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal-to-(noise + distortion) ratio (s/[n + d]) the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n + d) is expressed in decibels. aperture delay a measure of the acquisition performance, measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response the time required for the adc to achieve its rated accuracy after a full-scale step function is applied to its input. dac definition of specifications relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation in lsbs from a straight line passing through the endpoints of the dac transfer function. a typical inl versus code plot can be seen in tpc 16. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. tpc 19 illustrates a typical dnl versus code plot. gain error gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. it is the deviation in slope of the dac transfer characteristic from ideal. gain error temperature coefficient this is a measure of the change in gain error with changes in temperature. it is expressed in ppm/ c. zero code error zero code error is a measure of the output error when zero code is loaded to the dac register. zero code temperature coefficient this is a measure of the change in zero code error with a change in temperature. it is expressed in mv/ c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv? and is measured when the digital input code is changed by 1 lsb at the major carry transition. a plot of the glitch impulse is shown in figure 28. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. cs_dac is held high, while the clk and din signals are toggled. it is specified in nv? and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. a typical plot of digital feedthrough is shown in figure 27. power supply rejection ratio this specification indicates how the output of the dac is affected by changes in the power supply voltage. power supply rejection ratio is quoted in terms of percent change in output per percent change in v dd for full-scale output of the dac. v dd is varied by 10%. reference feedthrough this is a measure of the feedthrough from the v ref input to the dac output when the dac is loaded with all 0s. a 100 khz, 1v p-p is applied to v ref . reference feedthrough is expressed in mv p-p.
rev. a ad15700 ?5 16-bit d/a converter code 1.5 0 16384 32768 49152 65536 inl ?lsb 1.0 0.0 ?.5 ?.5 ?.5 0.5 ?.0 ?.0 2.0 2.5 tpc 1. integral nonlinearity vs. code code 1.25 0 16384 32768 49152 65536 dnl ?lsb 0.75 0.25 0.00 ?.50 ?.00 0.50 ?.25 ?.75 1.50 1.75 1.00 tpc 2. differential nonlinearity vs. code positive inl ?lsb 50 0.0 0.3 number of units 40 30 0 20 10 60 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 tpc 3. typical positive inl distribution (314 units) t ypical performance characteristics negative inl ?lsb 50 ?.0 ?.7 number of units 40 30 0 20 10 60 ?.4 ?.1 ?.8 ?.5 ?.2 ?.9 ?.6 ?.3 0.0 tpc 4. typical negative inl distribution (314 units) code in hexadecimal 7000 7ffd 7ffe counts 6000 5000 2000 4000 3000 8000 7fff 8000 8001 8002 8003 8004 8005 8006 8007 1000 0 1297 17 0 0 7029 7039 986 0 0 25 tpc 5. histogram of 16,384 conversions of a dc input at the code transition code in hexadecimal 9000 7ffc 7ffd counts 8000 7000 4000 6000 5000 10000 7ffe 8001 8002 8003 8004 8005 8006 8000 3000 0 2 0 00 0 1 2000 1000 7fff 8007 3296 9503 3344 106 132 tpc 6. histogram of 16,384 conversions of a dc input at the code center
rev. a ?6 ad15700 frequency ?khz 0 0 amplitude ?db of full scale ?0 ?0 ?00 ?0 ?0 ?20 ?80 ?40 ?60 100 200 300 400 500 fs = 1 msps f in = 45.5322khz snr = 89.45db thd = ?00.05db sfdr = 100.49db sinad = 89.1db tpc 7. fft plot frequency ?khz 95 0 snr and s/[n + d] ?db 90 85 80 70 75 10 100 1000 100 snr sinad enob 15.5 enob ?bits 15.0 14.5 14.0 13.0 13.5 16.0 tpc 8. snr, s/(n + d), and enob vs. frequency frequency ?khz 95 1 snr and s/[n + d] ?db 90 85 80 70 75 10 100 1000 100 snr sinad enob 15.5 enob ?bits 15.0 14.5 14.0 13.0 13.5 16.0 tpc 9. snr vs. input frequency temperature ? c 93 ?5 snr ?db 90 87 84 96 ?02 thd ?db ?04 ?8 ?00 ?06 525456 585 105 125 ?5 ?5 tpc 10. snr, thd vs. temperature frequency ?khz ?5 1 thd, harmonics ?db ?0 ?5 ?0 ?0 ?5 10 100 1000 ?0 105 sfdr ?db 95 85 75 60 65 115 ?5 ?00 ?10 ?05 ?15 110 100 90 80 70 sfdr thd third harmonic second harmonic tpc 11. thd, harmonics, and sfdr vs. frequency input level ?db ?0 ?0 thd, harmonics ?db ?0 ?0 ?50 ?00 ?10 ?0 ?0 ?0 ?0 ?0 ?0 0 ?30 ?40 ?20 thd second harmonic third harmonic tpc 12. thd, harmonics vs. input level
rev. a ad15700 ?7 c l ?pf 40 t 12 delay ?ns 30 0 20 10 50 050 100 150 200 tpc 13. typical delay vs. load capacitance c l sampling rate ?sps 10000 operating currents ?ma 1000 0.001 100 10 100000 010 100 1000 10000 0 0.1 0.01 100000 1000000 av dd, warp/normal dv dd, warp/normal av d d, impulse dvdd, impulse ovdd, all modes tpc 14. operating currents vs. sample rate temperature ? c 1000 ?5 power-down operating currents ?na 900 700 400 600 500 300 0 200 100 ?5 ?5 5 25 45 800 65 85 105 dvdd ovdd av d d tpc 15. power-down operating currents vs. temperature
rev. a ?8 ad15700 14-bit d/a converter code ?decimal 0.25 0 2048 inl ?lsb 0 ?.50 ?.25 0.50 4096 6144 8192 10240 12288 14336 16384 t a = 25 c v dd = 5v v ref = 2.5v tpc 16. integral nonlinearity vs. code temperature ? c 0.50 inl ?lsb 0.25 ?.50 0 ?.25 ?0 20 60 100 140 ?0 v dd = 5v v ref = 2.5v tpc 17. integral nonlinearity vs. temperature supply voltage ?v 0.75 2 linearity error ?lsb 0.50 0.25 ?.00 0 1.00 34 567 ?.50 ?.75 ?.25 dnl inl v dd = 2.5v t a = 25 c tpc 18. linearity error vs. supply voltage code ?decimal 0.25 0 2048 dnl ?lsb 0 ?.50 ?.25 0.50 4096 6144 8192 10240 12288 14336 16384 t a = 25 c v dd = 5v v ref = 2.5v tpc 19. differential nonlinearity vs. code temperature ? c 0.50 dnl ?lsb 0.25 ?.50 0 ?.25 ?0 20 60 100 140 ?0 v dd = 5v v ref = 2.5v tpc 20. differential nonlinearity vs. temperature reference voltage ?v 0.50 linearity error ?lsb 0.25 ?.50 0 ?.25 02345 16 v dd = 5v t a = 25 c dnl inl tpc 21. linearity error vs. reference voltage
rev. a ad15700 ?9 temperature ? c 0.75 ?0 ?5 gain error ?lsb 0.50 0.25 ?.50 0 ?.25 1.00 0255075 100 125 150 ?.75 ?.00 v dd = 5v v ref = 2.5v tpc 22. gain error vs. temperature temperature ? c ?0 ?0 supply current ?ma 200 250 0204 06080 100 120 150 v dd = 5v v logic = 5v v ref = 2.5v tpc 23. supply current vs. temperature digital input voltage ?v 01 supply current ?ma 350 400 2345 150 v dd = 5v v ref = 2.5v t a = 25 c 250 300 200 tpc 24. supply current vs. digital input voltage temperature ? c ?0 ?5 zero-code offset error ?lsb 0.75 0255075 0 v dd = 5v v ref = 2.5v 0.50 0.25 100 125 150 tpc 25. zero-code error vs. temperature vo ltag e ?v 01 supply current ?ma 350 400 2345 150 250 300 200 450 6 reference vo ltag e v dd = 5v supply vo ltag e v ref = 2.5v t a = 25 c tpc 26. supply current vs. reference voltage or supply voltage code ?decimal 250 0 2048 reference current ?ma 200 100 150 300 4096 6144 8192 10240 12288 14336 16384 t a = 25 c v dd = 5v v ref = 2.5v 0 50 tpc 27. reference current vs. code
rev. a ?0 ad15700 v ds ?mv 80 ? ? number of parts in bin 70 60 40 50 90 ? 012345 ? 30 0 20 10 ? 6 n = 250 tpc 28. typical v os distribution @ v s = 5 v temperature ? c 2.3 ?0 0 offset voltage ? mv 2.1 1.9 1.5 1.7 2.5 10 30 40 50 60 70 80 90 20 ?0 ?0 ?0 v s = 5v v s = 65v tpc 29. input offset voltage vs. temperature temperature ? c 0.95 ?0 0 input bias ?ma 0.90 0.85 0.75 0.80 1.00 10 30 40 50 60 70 80 90 20 ?0 ?0 ?0 v s = 5v 0.65 0.60 0.55 0.50 0.70 tpc 30. input bias current vs. temperature common-mode voltage ?v 600 01 input bias current ?na 400 ?00 200 0 800 2 56 7 89 4 ?00 ?00 ?00 310 v s = 10v v s = 5v v s = 2.7v tpc 31. input bias current vs. common-mode voltage common-mode voltage ?v ?.1 0 0.5 offset voltage ? mv ?.2 ?.3 ?.6 ?.4 ?.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v s = 5v tpc 32. v os vs. common-mode voltage temperature ? c 950 ?0 0 supply current/amplifier ?ma 900 850 750 800 1000 10 30 40 50 60 70 80 90 20 ?0 ?0 ?0 650 600 700 i s = 5v i s = 5v i s = 2.7v tpc 33. supply current vs. temperature
rev. a ad15700 ?1 amplifier r load ? 0 difference from v cc ?v ?.5 ?.5 ?.0 ?.5 100 1k 10k ?.0 v cc = 2.7v v cc = 5v v cc = 10v v cc v in v cc 2 v ee r load v out tpc 34. +output saturation voltage vs. r load @ 85 c r load ? 0 difference from v cc ?v ?.5 ?.5 ?.0 ?.5 100 1k 10k ?.0 v cc v in v cc 2 v ee r load v cc = 2.7v v cc = 5v v cc = 10v v out tpc 35. +output saturation voltage vs. r load @ 25 c r load ? 0 difference from v cc ?v ?.5 ?.5 ?.0 ?.5 100 1k 10k ?.0 v cc v in v cc 2 v ee r load v cc = 2.7v v cc = 5v v cc = 10v v out tpc. 36 +output saturation voltage vs. r load @ ?0 c r load ? 1.2 difference from v ee ?v 1.0 0 0.8 0.6 100 1k 10k 0.4 v cc v in v cc 2 v ee r load v cc = 2.7v v cc = 5v v cc = 10v v out 0.2 tpc 37. ?utput saturation voltage vs. r load @ 85 c r load ? 1.2 difference from v ee ?v 1.0 0 0.8 0.6 100 1k 10k 0.4 v cc v in v cc 2 v ee r load v cc = 2.7v v cc = 5v v cc = 10v v out 0.2 tpc 38. ?utput saturation voltage vs. r load @ 25 c r load ? 1.2 difference from v ee ?v 1.0 0 0.8 0.6 100 1k 10k 0.4 v cc v in v cc 2 v ee r load v cc = 2.7v v cc = 5v v cc = 10v v out 0.2 tpc. 39 ?utput saturation voltage vs. r load @ ?0 c
rev. a ?2 ad15700 r load ? 110 gain ?db 105 100 85 95 90 80 65 75 70 2k 4k 60 6k 8k 10k 0 v s = 5v ? ol +a ol tpc 40. open-loop gain (a ol ) vs. r load temperature ? c 84 ?0 0 gain ?db 82 80 76 78 86 10 30 40 50 60 70 80 90 20 ?0 ?0 ?0 v s = 5v r l = 1k ? ol +a ol tpc 41. open-loop gain (a ol ) vs. temperature v out ?v 100 0 0.5 a ol ?db 90 80 50 70 60 110 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 v s = 5v r load = 10k r load = 1k tpc 42. open-loop gain (a ol ) vs. v out input voltage v ?.5 input bias current ?ma 10 0 ?0 0.5 2.5 4.5 6.5 100 90 0% 10 500mv 500mv v s = 5v 1v tpc 43. differential input voltage 1 v characteristics 0.00 1st 2nd diff phase ?degrees ?.05 ?.10 0.10 ?.15 0.05 3rd 6th 7th 8th 9th 10th 11th 5th 0.05 ?.10 0.00 ?.05 4th 1st 2nd 3rd 6th 7th 8th 9th 10th 11th 5th 4th diff gain ?% tpc 44. differential gain and phase @ v s = 5 v; r l = 1 k w frequency ?hz input voltage noise ?nv/ hz 0.3 100 30 10 100 1k 10k 10 3 1 100k 10m 1m 100 10 1 0.1 vo lta ge noise current noise input current noise ?pa/ hz v s = 5v tpc 45. input voltage noise vs. frequency
rev. a ad15700 ?3 frequency ?mhz 4 0.1 1 10 100 normalized gain ?db 2 0 ? ? ? 1 ? ? 5 3 v s = 5v g = +1 r l = 1k tpc 46. unity gain, ? db bandwidth frequency ?mhz 2 0.1 1 10 100 normalized gain ?db ? ? ? ? 0 ? 3 1 v out 50 2k v s v in v s = 5v v in = ?6dbm +85 c +25 c ?0 c tpc 47. closed-loop gain vs. temperature frequency ?hz 1 closed-loop gain ?db ? ? ? ? ? ? ? ? 2 0 v s = 5v r l + c l to 2.5v g = +1 c l = 5pf r l = 1k v s = ?.7v r l + c l to 1.35v v s = 65v 10k 1m 10m 100m tpc 48. closed-loop gain vs. supply voltage frequency ?mhz phase ?degree ?0 ?80 ?35 ?25 0.3 110 100 40 30 20 10 0 ?0 ?0 open-loop gain ?db gain phase tpc 49. open-loop frequency response fundamental frequency ?hz ?0 to ta l harmonic distortion ?dbc ?0 ?0 ?0 ?0 ?0 ?0 1k 10k 100k 10m 1m g = +1, r l = 2k to v cc 2 2.5v p-p v s = 2.7v 1.3v p-p v s = 2.7v 4.8v p-p v s = 5v 2v p-p v s = 2.7v tpc 50. total harmonic distortion vs. frequency; g = +1 fundamental frequency ?hz ?0 to ta l harmonic distortion ?dbc ?0 ?0 ?0 ?0 ?0 ?0 1k 10k 100k 10m 1m ?0 ?00 g = +2 v s = 5v r l = 1k to v cc 2 4.6v p-p 4.8v p-p 4v p-p 1v p-p tpc 51. total harmonic distortion vs. frequency; g = +2
rev. a ?4 ad15700 fundamental frequency ?hz output ?v p-p 6 4 10 2 1k 10k 100k 10m 1m 0 8 v s = 65v v s = 5v v s = 2.7v tpc 52. large signal response frequency ?mhz 0.1 1 10 100 r out ? 50 1 0.1 10 100 v out rb rb t = 50 rb t = 0 200 tpc 53. r out vs. frequency frequency ?hz common-mode rejection ratio ?db ?0 0 ?0 ?0 ?0 ?00 v s = 5v 1k 10k 100k 10m 1m 100 tpc 54. cmrr vs. frequency frequency ?hz power supply rejection ratio ?db ?0 0 ?0 ?0 ?0 ?00 1k 10k 100k 10m 1m 100 100m ?20 v s = 5v tpc 55. psrr vs. frequency 10 s/div 1v/div 2.5 4.5 3.5 1.5 0.5 ?.5 5.5 v s = 5v r l = 10k to 2.5v v in = 6v p-p g = +1 tpc 56. output voltage 10 s/div 1v/div 2.5 4.5 3.5 1.5 0.5 ?.5 5.5 input beyond rails v s = 5v g = +1 input = 650mv tpc 57. output voltage phase reversal behavior
rev. a ad15700 ?5 10 s/div 500mv/div 0 v s = 5v r l = 1kv g = ? r l to 2.5v r l to gnd tpc 58. output swing 50ns/div 200mv/div 2.5 2.9 2.7 2.3 2.1 1.9 3.1 g = +2 r f = r g = 2.5k r l = 2k c l = 5pf v s = 5v tpc 59. 1 v step response 10 s/div 500mv/div 1.35 2.35 1.85 0.85 0.35 2.85 v s = 27v r l = 1k g = ? r l to gnd r l to 1.35v tpc 60. output swing 50ns/div 20mv/div 2.50 2.54 2.52 2.48 2.44 2.56 2.46 g = +1 r f = 0 r l = 2k to 2.5v c l = 5pf to 2.5v v s = 5v tpc 61. 100 mv step response
rev. a ?6 ad15700 circuit operation the ad15700 contains precision components for interfacing analog i/o to a processor. configuration for particular applications can be made with short external interconnects under the device. + in2 ?n2 ra2 rb2 rc2 ina inb inc ind ingnd ref refgnd vref vdd_dac dgnd_dac a gnd_dac v out_dac ra1 rb1 rc1 + in1 ?n1 v out2 + vs2 ?s2 rpad2 sclk sdout busy cnvst ob/ 2c ser/ par w arp rdc/sin invsclk invsync ext/ int divsclk1 divsclk0 impulse cs_adc rd byteswap reset pd sclk cs_dac din rpad1 v out1 + vs1 ?s1 state machine dsp/ p op amp resistor dac adc op-amp resistor tclk ad15700 analog input (0.2v to 2ref) analog output (0.2v to 2ref) +vs +vs dvdd ovdd ognd dgnd_adc dvdd av d d a gnd_adc digital supply (3.3v or 5v) analog supply (5v) c2 note 2 0.1 f 0.1 f 0.1 f 47 f c1 note 1 dgnd a gnd 0.1 f 10 f 100 rfs tfs rclk 0.1 f adr421 or ad780 2.5v or 3.0v ref notes 1. c1 forms an r-c filter with the 6.25k nominal output resistance of the dac 2. c2 forms part of the adc input filter. see analog input section. figure 4. typical connection diagram typical connection diagram figure 4 shows how, using a minimum of external devices, the com- ponents w ithin the ad15700 can be interconnected to form a complete analog interface to a processor. the circuit implements signal conditioning that includes buffering, filtering, and voltage scaling.
rev. a ad15700 ?7 analog input section made up of a buffer amplifier, an rc filter, and an adc, the analog input circuit allows measurement of voltages ranging from 0.2 v to 2 ref v. when placed in the 0 v to ref input range, the circuit has the configuration shown in figure 5a. adc 277 60pf c2 analog input 1.5k 1.5k figure 5a. analog input circuit the filter is made up of one of the ad15700? internal center- tapped resistors, an external capacitor c 2, plus the adc? internal resistance and capacitance. the transfer function of this filter is given by: hs sc s sc () = + ++ 8 11425 10 1 62285 10 202 288 2 1 21714 10 2 6 72 10 . ... with c2 set to 100 pf, the bandwidth is 1.2 mhz. without c2, the bandwidth of the filter is 2.6 mhz. to utilize the adc? maximum 9.6 mhz bandwidth, the components external to the adc are eliminated. in this case, the adc is configured for its 0 to 2 ref input range and the resulting equivalent input circuit is shown in figure 5b. adc 375 60pf analog input 375 100 figure 5b. analog input circuit analog output section the output circuitry consists of a dac, rc filter, and an amplifier. the circuit uses the dac? output resistance of 6.25 k w 20% to form a single-pole rc filter with an external capacitor c1. one of the ad15700? internal center-tapped resistors and one of its op amps form an amplifier with a gain of two. the gain is used to bring the dac? maximum range of ref volts up to 2 ref v. dac 6.25k 1.5k analog output c1 1.5k figure 6. analog output circuit voltage reference input the ad15700 uses an external 2.5 v or 3.0 v voltage reference. because of the dynamic input impedance of the a/d and the code dependent impedance of the d/a, the reference inputs must be driven by a low impedance source. decoupling consisting of a parallel combination of 47 m f and 0.1 m f capacitors is recom- mended. suitable references include the adr421 for 2.5 v output and the ad780 for selectable 2.5 v or 3.0 v output. both of these feature low noise and low temperature drift. processor interface the circuit in figure 5a uses serial interfacing to minimize the number of signals that connect to the digital circuits. external logic such as a state machine is used to generate clocks and other timing signals for the interface. ideally, the clocks supplied to the converters are discontinuous and operate at the maximum frequency supported by the converter and the processor. discontinuous clocks that are quiet during critical times minimize degradation caused by voltage transients on the digital interface. it is best to keep the clocks quiet during adc conversion and when the dac output is sampled by the external system. often, the processor cannot tolerate a discontinuous clock and therefore a separate continuous clock (or clocks) that is synchronous with the converter clocks must be generated. separate clocks for the dac and adc are used to maximize the data transfer rate to each converter. the adc operates at a maximum rate of 40 mhz while the dac can operate up to 25 mhz. adc circuit information the adc is a fast, low power, single-supply precise 16-bit analog- to-digital converter (adc). it features different modes to optimize performances according to the applications. in warp mode, it is capable of converting 1,000,000 samples per second (1 msps). the adc provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. it is specified to operate with both bipolar and unipolar input ranges by changing the connection of its input resistive scaler. the adc can be operated from a single 5 v supply and be inter- faced to either 5 v or 3 v digital logic. adc converter operation the adc is a successive approximation analog-to-digital con- verter based on a charge redistribution dac. figure 7 shows the simplified schematic of the adc. the input analog signal is first scaled down and level-shifted by the internal input resistive scaler, which allows both unipolar ranges (0 v to 2.5 v, 0 v to 5 v, and 0 to 10 v) and bipolar ranges ( 2.5 v, 5 v, and 10 v). the output voltage range of the resistive scaler is always 0 v to 2.5 v. the capacitive dac consists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparator? negative input is connected to a ?ummy?capacitor of the same value as the capacitive dac array. during the acquisition phase, the common terminal of the array tied to the comparator? positive input is connected to agnd via swa. all independent switches are connected to the output of the resistive scaler. thus, the capacitor array is used as a sampling capacitor and acquires the analog signal. similarly, the dummy capacitor acquires the analog signal on ingnd input. when the acquisition phase is complete, and the cnvst input goes or is low, a conversion phase is initiated. when the conversion phase begins, swa and swb are opened first. the capacitor array and the dummy capacitor are then disconnected from the inputs and connected to the refgnd input. therefore, the differ- ential voltage between the output of the resistive scaler and ingnd captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced.
rev. a ?8 ad15700 by switching each element of the capacitor array between refgnd or ref, the comparator input varies by binary weighted voltage steps (vref/2, vref/4. . .vref/65536). the control logic toggles these switches, starting with the msb first, in order to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and brings busy output low. modes of operation the adc features three modes of operation: warp, normal, and impulse. each of these modes is more suitable for specific applications. the warp mode allows the fastest conversion rate up to 1 msps. however, in this mode and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms. if the time between two con- secutive conversions is longer than 1 ms, for instance, after power-up, the first conversion result should be ignored. this mode makes the adc ideal for applications where both high accuracy and fast sample rate are required. the normal mode is the fastest mode (800 ksps) without any limitation about the time between conversions. this mode makes the adc ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. the impulse mode, the lowest power dissipation mode, allows power saving between conversions. the maximum throughput control logic ind inc inb ina 4r 4r 2r r ref refgnd ingnd 32768c 16384c msb 4c 2c c lsb sw a c 65536c sw b switches control busy output code cnvst comp figure 7. adc simplified schematic in this mode is 666 ksps. when operating at 100 sps, for example, it typically consumes only 15 m w. this feature makes the adc ideal for battery-powered applications. transfer functions using the ob/2c digital input, the adc offers two output codings: straight binary and twos complement. the ideal transfer characteristic for the adc is shown in figure 8 and table iii. 111...101 111...111 111...110 000...000 000...010 000...001 analog input adc code ?straight binary ?s + 0.5lsb ?s + 1lsb ?s +fs ?1.5lsb +fs ?1lsb figure 8. adc ideal transfer function table iii. output codes and ideal input voltages digital output code (hexadecimal) straight twos description analog input binary complement full-scale range 10 v 5 v 2.5 v 0 v to 10 v 0 v to 5 v 0 v to 2.5 v least significant bit 305.2 m v 152.6 m v 76.3 m v 152.6 m v 76.3 m v 38.15 m v fsr ? lsb 9.999695 v 4.999847 v 2.499924 v 9.999847 v 4.999924 v 2.499962 v ffff 1 7fff 1 midscale +1 lsb 305.2 m v 152.6 m v 76.3 m v 5.000153 v 2.570076 v 1.257038 v 8001 0001 midscale 0 v 0 v 0 v 5 v 2.5 v 1.25 v 8000 0000 midscale ? lsb ?05.2 m v ?52.6 m v ?6.3 m v 4.999847 v 2.499924 v 1.249962 v 7fff ffff ?sr +1 lsb ?.999695 v ?.999847 v ?.499924 v 152.6 m v 76.3 m v 38.15 m v 0001 8001 ?sr ?0 v ? v ?.5 v 0 v 0 v 0 v 0000 2 8000 2 notes 1 this is also the code for an overrange analog input. 2 this is also the code for an underrange analog input.
rev. a ad15700 ?9 analog inputs the adc is specified to operate with six full-scale analog input ranges. connections required for each of the four analog inputs, ind, inc, inb, ina, and the resulting full-scale ranges are shown in table i. the typical input impedance for each analog input range is also shown. figure 9 shows a simplified analog input section of the adc. ind inc inb ina av d d a gnd r = 1.28k c s r1 4r 4 2r r figure 9. simplified analog input the four resistors connected to the four analog inputs form a resistive scaler that scales down and shifts the analog input range to a common input range of 0 v to 2.5 v at the input of the switched capacitive adc. by connecting the four inputs ina, inb, inc, and ind to the input signal itself, the ground, or a 2.5 v reference, other analog input ranges can be obtained. the diodes shown in figure 9 provide esd protection for the four analog inputs. the inputs inb, inc, and ind, have a high voltage protection (?1 v to +30 v) to allow wide input voltage range. care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs including ina (0 v to 5 v). this will cause these diodes to become for- ward-biased and start conducting current. these diodes can handle a forward-biased current of 120 ma maximum. for instance, when using the 0 v to 2.5 v input range, these condi- tions could eventually occur on the input ina when the input buffer? (u1) supplies are different from avdd. in such case, an input buffer with a short circuit current limitation can be used to protect the part. this analog input structure allows the sampling of the differential signal between the output of the resistive scaler and ingnd. unlike other converters, the ingnd input is sampled at the same time as the inputs. by using this differential input, small signals common to both inputs are rejected as shown in figure 10, which represents the typical cmrr over frequency. for instance, by using ingnd to sense a remote signal ground, differences of ground potentials between the sensor and the local adc ground are eliminated. during the acquisition phase for ac signals, the adc behaves like a one-pole rc filter consisting of the equivalent resistance of the resistive scaler r/2 in series with r1 and c s . the resistor r1 is typically 100 w and is a lumped component made up of some serial resistor and the on resistance of the switches. the capacitor c s is typically 60 pf and is mainly the adc sampling capacitor. this one-pole filter with a typical ? db cutoff frequency of 9.6 mhz reduces undesirable aliasing effects and limits the noise coming from the inputs. frequency ?khz 70 cmrr ?db 65 60 55 75 100 50 45 40 35 10 1 1000 10000 figure 10. analog input cmrr vs. frequency except when using the 0 v to 2.5 v analog input voltage range, the adc has to be driven by a very low impedance source to avoid gain errors. that can be done by using the driver amplifier. when using the 0 v to 2.5 v analog input voltage range, the input impedance of the adc is very high so the adc can be driven directly by a low impedance source without gain error. that allows putting an external one-pole rc filter between the output of the amplifier output and the adc analog inputs to even further improve the noise filtering done by the adc analog input circuit. however, the source impedance has to be kept low because it affects the ac performances, especially the total harmonic distortion (thd). the maximum source impedance depends on the amount of total thd that can be tolerated. the thd degra- dation is a function of the source impedance and the maximum input frequency, as shown in figure 11. frequency ?khz thd ?db ?0 ?0 ?0 100 ?00 ?10 0 1000 r = 50 r = 100 r = 11 figure 11. thd vs. analog input frequency and input resistance (0 v to 2.5 v only)
rev. a ?0 ad15700 driver amplifier choice although the adc is easy to drive, the driver amplifier needs to meet at least the following requirements: the driver amplifier and the adc analog input circuit must be able, together, to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transi tion noise performance of the adc. the noise coming from the driver is first scaled down by the resistive scaler according to the analog input voltage range used, and is then filtered by the adc analog input circuit one-pole, low-pass filter made by (r/2 + r1) and cs. the snr degradation due to the amplifier is: snr f ne fsr loss db n = + ? ? ? ? ? ? ? ? ? ? ? log 28 784 2 25 3 2 p . where: f ? db is the ? db input bandwidth in mhz of the adc (9.6 mhz) or the cutoff frequency of the input filter if any is used (0 v to 2.5 v range). n is the noise factor of the amplifier (1 if in buffer configuration). e n is the equivalent input noise voltage of the op amp in nv/ hz . fsr is the full-scale span (i.e., 5 v for 2.5 v range). for instance, when using the 0 v to 5 v range, a driver like the ad15700? internal op amp, with an equivalent input noise of 15 nv/ hz and configured as a buffer, followed by a 3.2 mhz rc filter, the snr degrades by about 1.3 db. the driver needs to have a thd performance suitable to that of the adc. figure 11 gives the thd versus fre quency that the driver should preferably exceed. voltage reference input the adc uses an external 2.5 v voltage reference. the voltage reference input ref of the adc has a dynamic input impedance. therefore, it should be driven by a low impedance source with an efficient decoupling between ref and refgnd inputs. this decoupling depends on the choice of the voltage reference, but usually consists of a low esr tantalum capacitor connected to the ref and refgnd inputs with minimum parasitic inductance. 47 m f is an appropriate value for the tantalum capacitor when used with one of the recommended reference voltages: the low noise, low temperature drift adr421 or ad780 voltage references the low power adr291 voltage reference the low cost ad1582 voltage reference care should also be taken with the reference temperature coefficient of the voltage reference, which directly affects the full-scale accuracy if this parameter matters. for instance, a 15 ppm/ c tempco of the reference changes the full scale by 1 lsb/ c. scaler reference input (bipolar input ranges) when using the adc with bipolar input ranges, a buffer amplifier is required to isolate the refin pin from the signal dependent current in the ain pin. a high speed op amp can be used with a single 5 v power supply without degrading the performance of the adc. the buffer must have good settling characteristics and provide low total noise within the input bandwidth of the adc. power supply the adc uses three sets of power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.7 v and 5.25 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply. the adc is independent of power supply sequencing and thus free from supply voltage induced latchup. additionally, it is very insensitive to power supply variations over a wide frequency range, as shown in figure 12. frequency ?khz 70 65 60 55 75 50 45 40 psrr ?db 100 35 10 1 1000 10000 figure 12. psrr vs. frequency power dissipation in impulse mode, the adc automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low, which allows a significant power savings when the conversion rate is reduced, as shown in figure 13. this feature makes the adc ideal for very low power battery applications. this does not take into account the power, if any, dissipated by the input resistive scaler, which depends on the input voltage range used and the analog input voltage even in power-down mode. there is no power dissipated when the 0 v to 2.5 v is used or when both the analog input voltage is 0 v and a unipolar range, 0 v to 5 v or 0 v to 10 v, is used. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., dvdd and dgnd) and ovdd should not exceed dvdd by more than 0.3 v.
rev. a ad15700 ?1 sampling rate ?sps 10000 1000 100 100000 10 1 power dissipation ?mw 10 0.1 1 100 1000 10000 100000 1000000 w arp/normal impulse figure 13. power dissipation vs. sample rate conversion control figure 14 shows the detailed timing diagrams of the conversion process. the adc is controlled by the signal cnvst , which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input pd, until the conver- sion is complete. the cnvst signal operates independently of cs_adc and rd signals. convert ac q uire ac q uire convert t 2 t 4 t 8 t 6 t 3 t 5 t 1 c nvst busy mode t 7 figure 14. basic conversion timing in impulse mode, conversions can be automatically initiated. if cnvst is held low when busy is low, the adc controls the acquisition phase and then automatically initiates a new conversion. by keeping cnvst low, the adc keeps the conversion process running by itself. it should be noted that the analog input has to be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the adc could sometimes run slightly faster than the guaranteed limits in the impulse mode of 666 ksps. this feature does not exist in warp or normal modes. although cnvst is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. it is a good thing to shield the cnvst trace with ground and also to add a low value serial resistor (i.e., 50 w ) termination close to the output of the com- ponent that drives this line. for applications where the snr is critical, cnvst signal should have a very low jitter. one way to achieve that is to use a dedicated oscillator for cnvst generation, or at least to clock it with a high frequency low jitter clock. t 9 t 8 cnvst data busy reset figure 15. reset timing digital interface the adc has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the adc digital interface also accommodates both 3 v or 5 v logic by simply connecting the ovdd supply pin of the adc to the host system interface digital supply. finally, by using the ob/ 2c input pin, both straight binary or twos complement coding can be used. the two signals, cs_adc and rd , control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs_adc allows the selection of each adc in multicircuit applications and is held low in a single adc design. rd is generally used to enable the conversion result on the data bus. previous conversion data new data data bus busy cnvst cs_adc = rd = 0 t 1 t 10 t 4 t 11 t 3 figure 16. master parallel data timing for reading (continuous read)
rev. a ?2 ad15700 parallel interface the adc is configured to use the parallel interface when the ser/ par is held low. the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in figures 18 and 19. when the data is read during the conversion, however, it is recommended that it be read only during the first half of the conversion phase. that avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. current conversion csz_adc rd busy data bus t 12 t 13 figure 17. slave parallel data timing for reading (read after convert) previous conversion t 13 t 12 t 3 t 4 t 1 cs_adc = 0 cnvst , rd busy data bus figure 18. slave parallel data timing for reading (read during convert) the byteswap pin allows a glueless interface to an 8-bit bus. as shown in figure 19, the lsb byte is output on d[7:0] and the msb is output on d[15:8] when byteswap is low. when byteswap is high, the lsb and msb are swapped and the lsb is output on d[15:8] and the msb is output on d [7:0]. by connecting byteswap to an address line, the 16 data bits can be read in two bytes on either d[15:8] or d[7:0]. high byte low byte t 13 t 12 cs_adc high byte low byte hi-z hi-z hi-z hi-z rd byte pins d[15.8] pins d[7.0] t 12 figure 19. 8-bit parallel interface serial interface the adc is configured to use the serial interface when the ser/ par is held high. the adc outputs 16 bits of data, msb first, on the sdout pin. this data is synchronized with the 16 clock pulses provided on the sclk pin. the output data is valid on both the rising and falling edge of the data clock. master serial interface internal clock the adc is configured to generate and provide the serial data clock sclk when the ext/int pin is held low. it also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. depending on rdc/sdin input, the data can be read after each conversion or during conversion. figures 20 and 21 show the detailed timing diagrams of these two modes. usually, because the adc is used with a fast throughput, the mode master read during conversion is the most recommended serial mode when it can be used. in read during conversion mode, the serial clock and data toggle at appropriate instants, which minimizes potential feedthrough between digital activity and the critical conversion decisions. in read after conversion mode, it should be noted that unlike in other modes, the signal busy returns low after the 16 data bits are pulsed out and not at the end of the conversion phase, which results in a longer busy width. slave serial interface external clock the adc is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. the external serial clock is gated by cs_adc and the data are output when both cs_adc and rd are low. thus, depending on cs_adc , the data can be read after each conversion or during the following conversion. the external clock can be either a continuous or discontinuous clock. a discontinuous clock can be either normally high or normally low when inactive. figure 22 and figure 24 show the detailed timing diagrams of these methods.
rev. a ad15700 ?3 13 14 15 16 2 d15 d14 d2 d1 d0 x t 16 t 22 t 23 t 15 t 14 t 29 t 18 t 19 t 21 t 20 t 28 t 30 t 24 t 26 t 25 t 27 t 3 cs_adc , rd cnvst busy sync sclk sdout ext/ int = 0 rdc/sdin = 0 invsclk = invsync = 0 figure 20. master serial data timing for reading (read after convert) ext/ int = 0 rdc/sdin = 1 invsclk = invsync = 0 d15 d14 d2 d1 d0 x 13 14 15 16 2 t 24 t 26 t 25 t 27 t 16 t 22 t 23 cs_adc , rd cnvst busy sync sclk sdout t 21 t 20 t 19 t 3 t 1 t 14 t 15 t 18 t 17 figure 21. master serial data timing for reading (read previous conversion during convert) cs_adc , rd busy sdin sclk sdout 1 3 14 15 16 2 17 18 x14 x15 d0 d13 d1 d14 d15 x y14 y15 x0 x13 x1 x14 x15 t 16 t 34 t 31 t 32 t 35 t 37 t 36 t 33 ext/ int = 1 rd = 0 invsclk = 0 figure 22. slave serial data timing for reading (read after convert)
rev. a ?4 ad15700 while the adc is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. this is particu- larly im portant during the second half of the conversion phase because the adc provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when busy is low or, more importantly, that it does not transition during the latter half of busy high. external discontinuous clock data read after conversion though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. figure 22 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the result of this conversion can be read while both cs_adc and rd are low. the data is shifted out, msb first, with 16 clock pulses and is valid on both the rising and falling edge of the clock. among the advantages of this method is that the conversion perfor- mance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advan- tage is to be able to read the data at any speed up to 40 mhz, which accommodates both slow digital host interface and the fastest serial reading. finally, in this mode only, the adc provides a daisy-chain feature using the rdc/sdin input pin for cascading multiple converters together. this feature is useful for reducing compo nent count and wiring connections when desired as, for instance, in isolated multiconverter applications. an example of the concatenation of two devices is shown in figure 23. simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the opposite edge of sclk of the one used to shift out the data on sdout. therefore, the msb of the ?pstream converter just follows the lsb of the ?ownstream?converter on the next sclk cycle. ad15700 n o. 1 (downstream) ad15700 n o. 2 (upstream) data out busy out busy busy cs_adc in cnvst in sclk in rdc/sdin sdout rdc/sdin cnvst cnvst cs_adc sclk cs_adc sclk sdout figure 23. two ad15700s in a daisy-chain configuration external clock data read during conversion figure 24 shows the detailed timing diagrams of this method. during a conversion, while both cs_adc and rd are low, the result of the previous conversion can be read. the data is shifted out, msb first, with 16 clock pulses and is valid on both the rising and falling edge of the clock. the 16 bits have to be read before the current conversion is complete. if that is not done, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy-chain feature in this mode and rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock of at least 25 mhz when impulse mode is used, and 32 mhz when normal or 40 mhz when warp mode is used, is recommended to ensure that all the bits are read during the first half of the conversion phase. it is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. that allows the use of a slower clock speed like 18 mhz in impulse mode, 21 mhz in normal mode, and 26 mhz in warp mode. d13 d14 d15 x d1 d0 1 3 14 15 16 2 t 3 t 35 t 37 t 36 t 31 t 32 t 16 cs_adc busy sclk sdout cnvst ext/ int = 1 rd = 0 invsclk = 0 figure 24. slave serial data timing for reading (read previous conversion during convert)
rev. a ad15700 ?5 microprocessor interfacing the adc is ideally suited for traditional dc measurement appli- cations supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. the adc is designed to interface either with a parallel 8-bit or 16-bit wide interface or with a general-purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the adc to prevent digital noise from coupling into the adc. the following sections illustrate the use of the adc with an spi equipped microcontroller, the adsp-21065l and adsp-218x signal processors. spi interface (mc68hc11) figure 25 shows an interface diagram between the adc and an spi equipped microcontroller like the mc68hc11. to accommodate the slower speed of the microcontroller, the adc acts as a slave device and data must be read after conversion. this mode also allows the daisy-chain feature. the convert command could be initiated in response to an internal timer interrupt. the reading of output data, one byte at a time, if necessary, could be initiated in response to the end-of-conversion signal (busy going low) using an interrupt line of the microcontroller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1, and spi interrupt enable (spie) = 1 by writing to the spi control register (spcr). the irq is configured for edge-sensitive-only operation (irqe = 1 in option register). ad15700 * busy invsclk sdout cnvst sclk mc68hc11 * irq mso/sdi i/o port sck * additional pins omitted for clarity rd cs_adc ext/ int ser/ par dvdd figure 25. interfacing the ad15700 to spi interface adsp-21065l in master serial interface as shown in figure 26, ad15700s can be interfaced to the adsp-21065l using the serial interface in master mode without any glue logic required. this mode combines the advantages of reducing the wire connections and the ability to read the data during or after conversion at maximum speed transfer (divsclk[0:1] both low). the adc is configured for the internal clock mode (ext/ int low) and acts, therefore, as the master device. the convert com- mand can be generated by either an external low jitter oscillator or, as shown, by a flag output of the adsp-21065l or by a frame output tfs of one serial port of the adsp-21065l, which can be used like a timer. the serial port on the adsp-21065l is configured for external clock (irfs = 0), rising edge active (ckre = 1), external late framed sync signals (irfs = 0, lafs = 1, rfsr = 1), and active high (lrfs = 0). the serial port of the adsp-21065l is configured by writing to its receive control register (srctl)?ee the adsp-2106x sharc user? manual . because the serial port within the adsp-21065l will be seeing a discontinuous clock, an initial word reading has to be done after the adsp-21065l has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation. ad15700 * sync invsclk sdout cnvst sclk adsp-21065l * sharc rfs dr flag or tfs rclk * additional pins omitted for clarity rd cs_adc rdc/sdin ser/ par dvdd invsync ext/ int figure 26. interfacing to the adsp-21065l using the serial master mode application hints layout the ad15700? adc has very good immunity to noise on the power supplies as can be seen in figure 12. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad15700 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the ad15700, or at least as close as possible to the ad15700. if the ad15700 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the ad15700. it is recom- mended to avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of feedthrough through the board. the power supply lines to the ad15700 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also impor- tant to lower the supply impedance presented to the ad15700 and reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supply pin, avdd, dvdd, and ovdd, close to and ideally right up against these pins and their corresponding ground pins. additionally, low esr 10 nf capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. the dvdd supply of the ad15700 can be either a separate supply or come from the analog supply, avdd, or from the digital interface supply, ovdd. when the system digital supply is noisy, or fast switching digital signals are present, it is recommended if no separate supply is available to connect the dvdd digital supply to the analog supply avdd through an rc filter, and connect the system supply to the interface digital supply ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes.
rev. a ?6 ad15700 the ad15700? adc has five different ground pins: ingnd, refgnd, agnd, dgnd, and ognd. ingnd is used to sense the analog input signal. refgnd senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. agnd is the ground to which most internal adc analog signals are referenced. this ground must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the configuration. ognd is connected to the digital system ground. the layout of the decoupling of the reference voltage is important. the decoupling capacitor should be close to the adc and connected with short and large traces to minimize parasitic inductances. 100 90 0% 10 v ref = 2.5v v dd = 5v t a = 25 c 2 s /div v out = (50mv/div) clock (5v/div) figure 27. digital feedthrough 100 90 0% 10 v ref = 2.5v v dd = 5v t a = 25 c 2 s /div cs (5v/div) v out (0.1v/div) figure 28. digital-to-analog glitch impulse 100 90 0% 10 2 s /div v ref = 2.5v v dd = 5v t a = 25 c 50pf 100pf 200pf 10pf cs (5v/div) v out (0.5v/div) figure 29. large signal settling time 100 90 0% 10 v out (1v/div) v out (50mv/div) gain = ?16 v ref = 2.5v v dd = 5v t a = 25 c 0.5 s/div figure 30. small signal settling time dac circuit information the dac is a single 14-bit, serial input voltage output. it operates from a single supply ranging from 2.7 v to 5 v and consumes typically 300 ma with a supply of 5 v. data is written to the devices in a 14-bit word format, via a 3- or 4-wire serial interface. to ensure a known power-up state, the parts were designed with a power-on reset function. in unipolar mode, the output is reset to 0 v. digital-to-analog section the dac architecture consists of two matched dac sections. a simplified circuit diagram is shown in figure 31. the four msbs of the 14-bit data-word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of 15 matched resistors to either agnd or vref. the remaining 10 bits of the data-word drive switches s0 to s9 of a 10-bit voltage mode r-2r ladder network. 2r 2r 2r 2r 2r 2r r s0 s1 s9 e1 e2 e15 r 2r v out 10-bit r-2r ladder four msbs decoded into 15 equal segments figure 31. dac architecture with this type of dac configuration, the output impedance is independent of code, while the input impedance seen by the reference is heavily code dependent. the output voltage is dependent on the reference voltage as shown in the following equation. v vd out ref n = 2 where d is the decimal data-word loaded to the dac register and n is the resolution of the dac. for a reference of 2.5 v, the equation simplifies to the following. v d out = 25 16 384 . , giving a v out of 1.25 v with midscale loaded, and 2.5 v with full scale loaded to the dac. the lsb size is v ref /16,384.
rev. a ad15700 ?7 serial interface the dac is controlled by a versatile 3-wire serial interface that operates at clock rates up to 25 mhz and is compatible with spi, qspi, microwire, and dsp interface standards. the timing diagram can be seen in figure 3. input data is framed by the chip select input, cs_dac . after a high to low transition on cs_dac , data is shifted synchronously and latched into the input register on the rising edge of the serial clock, sclk. data is loaded msb first in 14-bit words. after 14 data bits have been loaded into the serial input register, a low to high transition on cs_dac transfers the contents of the shift register to the dac. data can only be loaded to the part while cs_dac is low. unipolar output operation the dac is capable of driving unbuffered loads of 60 k w . unbuffered operation results in low supply current, typically 300 ma, and a low offset error. the dac provides a unipolar output swing ranging from 0 v to vref. figure 32 shows a typical unipolar output voltage circuit. the code table for this mode of operation is shown in table iv. dac dgnd a gnd sclk din cs v dd v ref serial interface unipolar output op amp 10 f 2.5v 5v 0.1 f 0.1 f out figure 32. unipolar output table iv. unipolar code table dac latch contents msb lsb analog output 11 1111 1111 1111 vref x (16383/16384) 10 0000 0000 0000 vref x (8192/16384) = 1/2 vref 00 0000 0000 0001 vref x (1/16384) 00 0000 0000 0000 0 v assuming a perfect reference, the worst-case output voltage may be calculated from the following equation. v d vvv inl out uni ref ge zse = + () ++ 2 14 where: v out ?ni = unipolar mode worst-case output d = decimal code loaded to dac v ref = reference voltage applied to part v ge = gain error in volts v zse = zero scale error in volts inl = integral nonlinearity in volts output amplifier selection in a single-supply application, selection of a suitable op amp may be more difficult as the output swing of the amplifier does not usually include the negative rail, in this case agnd. this can result in some degradation of the specified performance unless the application does not use codes near zero. the selected op amp needs to have very low offset voltage (the dac lsb is 152 m v with a 2.5 v reference) to eliminate the need for output offset trims. input bias current should also be very low as the bias current multiplied by the dac output impedance (approximately 6 k w ) will add to the zero code error. rail-to-rail input and output performance is required. for fast settling, the slew rate of the op amp should not impede the settling time of the dac. output impedance of the dac is constant and code independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as high as possible. the amplifier should also have a 3 db band- width of 1 mhz or greater. the amplifier adds another time constant to the system, thus increasing the settling time of the output. a higher 3 db amplifier bandwidth results in a faster effective settling time of the combined dac and amplifier. force sense buffer amplifier selection these amplifiers can be single-supply or dual-supply, low noise amplifiers. a low output impedance at high frequencies is pre- ferred to be able to handle dynamic currents of up to 20 ma. reference and ground as the input impedance is code dependent, the reference pin should be driven from a low impedance source. the dac oper- ates with a voltage reference ranging from 2 v to v dd . although dac? full-scale output voltage is determined by the reference, references below 2 v will result in reduced accuracy. table iv outlines the analog output voltage for particular digital codes. power-on reset the dac has a power-on reset function to ensure the output is at a known state upon power-up. on power-up, the dac register contains all zeros, until data is loaded from the serial register. however, the serial register is not cleared on power-up, so its contents are undefined. when loading data initially to the dac, 14 bits or more should be loaded to prevent erroneous data appearing on the output. if more than 14 bits are loaded, only the last 14 are kept, and if fewer than 14 are loaded, bits will remain from the previous word. if the dac needs to be interfaced with data shorter than 14 bits, the data should be padded with zeros at the lsbs. power supply and reference bypassing for accurate high resolution performance, it is recommended that the reference and supply pins be bypassed with a 10 nf tantalum capacitor in parallel with a 0.1 nf ceramic capacitor. microprocessor interfacing microprocessor interfacing to the dac is via a serial bus that uses standard protocol compatible with dsp processors and microcontrollers. the communications channel requires a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. the dac requires a 14-bit data-word with data valid on the rising edge of sclk. the dac update may be done automatically when all the data is clocked in.
rev. a ?8 ad15700 adsp-2101/adsp-2103 to dac interface figure 33 shows a serial interface between the dac and the adsp-2101/adsp-2103. the adsp-2101/adsp-2103 should be set to operate in the sport (serial port) transmit alternate framing mode. the adsp-2101/adsp-2103 is programmed through the sport control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. the first two bits are don? care as the dac will keep the last 14 bits. transmission is initiated by writing a word to the tx register after the sport has been enabled. because of the edge-triggered difference, an inverter is required at the sclks between the dsp and the dac. adsp-2101/ adsp-2103 * * additional pins omitted for clarity cs_dac din sclk sclk dt tfs dac figure 33. adsp-2101/adsp-2103 to dac interface 68hc11/68l11 to dac interface figure 34 shows a serial interface between the dac and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the dac, while the mosi output drives the serial data lines sdin. cs signal is driven from one of the port lines. the 68hc11/68l11 is configured for master mode; mstr = 1, cpol = 0, and cpha = 0. data appearing on the mosi output is valid on the rising edge of sck. 68hc11/ 68l11 * * additional pins omitted for clarity cs_dac din sclk sck mosi pc7 pc6 dac figure 34. 68hc11/68l11 to dac interface microwire to dac interface figure 35 shows an interface between the dac and any microwire compatible device. serial data is shifted out on the falling edge of the serial clock and into the dac on the rising edge of the serial clock. no glue logic is required as the dac clocks data into the input shift register on the rising edge. microwire * * additional pins omitted for clarity cs_dac din sclk sclk so dac figure 35. microwire to dac interface 80c51/80l51 to dac interface a serial interface between the dac and the 80c51/80l51 microcontroller is shown in figure 36. txd of the microcontroller drives the sclk of the dac, while rxd drives the serial data line of the dac. p3.3 is a bit programmable pin on the serial port that is used to drive cs_dac . 80c51/ 80l51 * * additional pins omitted for clarity dac cs_dac din sclk txd rxd p3.3 figure 36. 80c51/80l51 to dac interface the 80c51/80l51 provides the lsb first, while the dac expects the msb of the 14-bit word first. care should be taken to ensure the transmit routine takes this into account. usually it can be done through software by shifting out and accumulating the bits in the correct order before inputting to the dac. also, 80c51 outputs 2-byte word/16-bit data. thus the first two bits, after rearrangement, should be don? care as they will be dropped from the dac? 14-bit word. when data is to be transmitted to the dac, p3.3 is taken low. data on rxd is valid on the falling edge of txd, so the clock must be inverted as the dac clocks data into the input shift register on the rising edge of the serial clock. the 80c51/80l51 transmits its data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. as the dac requires a 14-bit word, p3.3 (or any one of the other programmable bits) is the cs_dac input signal to the dac, so p3.3 should be brought low at the beginning of the 16-bit write cycle 2 8-bit words and held low until the 16-bit 2 8 cycle is completed. after that, p3.3 is brought high again and the new data loads to the dac. again, the first two bits, after rearranging, should be don? care. applications optocoupler interface the digital inputs of the dac are schmitt-triggered, so they can accept slow transitions on the digital input lines. this makes these parts ideal for industrial applications where it may be necessary for the dac to be isolated from the controller via optocouplers. figure 37 illustrates such an interface. v dd 10k v dd 10k v dd 10k din cs sclk sclk cs_dac din gnd v dd v out dac power 0.1nf 10nf 5v regulator figure 37. dac in an optocoupler interface
rev. a ad15700 ?9 decoding multiple dacs the cs_dac pin of the dac can be used to select one of a number of dacs. all devices receive the same serial clock and serial data, but only one device will receive the cs_dac signal at any one time. the dac addressed will be determined by the decoder. there will be some digital feedthrough from the digital input lines. using a burst clock will minimize the effects of digital feedthrough on the analog signal channels. figure 38 shows a typical circuit. cs_dac v out dac sclk din sclk din enable coded address dgnd v dd decoder en cs_dac v out dac sclk din cs_dac v out dac sclk din cs_dac v out dac sclk din figure 38. addressing multiple dacs amplifier theory of operation the amplifiers are single and dual versions of high speed, low power voltage feedback amplifiers featuring an innovative archi- tecture that maximizes the dynamic range capability on the inputs and outputs. linear input common-mode range exceeds either supply voltage by 200 mv, and the amplifiers show no phase reversal up to 500 mv beyond supply. the output swings to within 20 mv of either supply when driving a light load; 300 mv when driving up to 5 ma. the amplifier provides an impressive 80 mhz bandwidth when used as a follower and 30 v/ms slew rate at only 800 ma supply current. careful design allows the amplifier to operate with a supply voltage as low as 2.7 v. input stage operation a simplified schematic of the input stage appears in figure 39. for common-mode voltages up to 1.1 v within the positive supply, (0 v to 3.9 v on a single 5 v supply) tail current i2 flows through the pnp differential pair, q13 and q17. q5 is cut off; no bias current is routed to the parallel npn differential pair q2 and q3. as the common-mode voltage is driven within 1.1 v of the positive supply, q5 turns on and routes the tail current away from the pnp pair and to the npn pair. during this transition region, the amplifier? input current will change magnitude and direction. reusing the same tail current ensures that the input stage has the same transconductance (which determines the amplifier? gain and bandwidth) in both regions of operation. switching to the npn pair as the common-mode voltage is driven beyond 1 v within the positive supply allows the amplifier to provide useful operation for signals at either end of the supply voltage range and eliminates the possibility of phase reversal for input signals up to 500 mv beyond either power supply. offset voltage will also change to reflect the offset of the input pair in control. the transition region is small, on the order of 180 mv. these sudden changes in the dc parameters of the input stage can produce glitches that will adversely affect distortion. ? ? 1.1v v in q5 q9 v ip r6 850 r7 850 q13 q17 q18 q4 q14 44 4 1 1 1 1 4 v ee i1 5ma i2 90ma i3 25ma i4 25ma q8 q6 q2 q3 r9 850 r8 850 r5 50k q15 q16 q11 q7 q10 r2 2k r4 2k r3 2k ? v cc r1 2k output stage, common-mode feedback ? figure 39. simplified schematic of input stage
rev. a ?0 ad15700 overdriving the input stage sustained input differential voltages greater than 3.4 v should be avoided as the input transistors may be damaged. input clamp diodes are recommended if the possibility of this condition exists. the voltages at the collectors of the input pairs are set to 200 mv from the power supply rails. this allows the amplifier to remain in linear operation for input voltages up to 500 mv beyond the supply voltages. driving the input common-mode voltage beyond that point will forward bias the collector junction of the input transistor, resulting in phase reversal. sustaining this condition for any length of time should be avoided as it is easy to exceed the maximum allowed input differential voltage when the amplifier is in phase reversal. output stage, open-loop gain, and distortion versus clearance from power supply the amplifier features a rail-to-rail output stage. the output transistors operate as common emitter amplifiers, providing the output drive current as well as a large portion of the amplifier? open-loop gain. i2 25ma i1 25ma i4 25ma i5 25ma differential drive from input stage v out r29 300 c9 1.5pf c5 1.5pf q49 q50 q44 q47 q51 q42 q20 q21 q43 q48 q68 q38 q37 q27 figure 40. output stage simplified schematic the output voltage limit depends on how much current the output transistors are required to source or sink. for applica- tions with very low drive requirements (a unity gain follower driving another amplifier input, for instance), the amplifier typically swings within 20 mv of either voltage supply. as the required current load increases, the saturation output voltage will increase linearly as i load r c , where i load is the required load current and r c is the output transistor collector resistance. for the amplifier, the collector resistances for both output tran- sistors are typically 25 w . as the current load exceeds the rated output current of 15 ma, the amount of base drive current required to drive the output transistor into saturation will reach its limit, and the amplifier? output swing will rapidly decrease. the open-loop gain of the amplifier decreases approximately linearly with load resistance and also depends on the output voltage. open-loop gain stays constant to within 250 mv of the positive power supply, 150 mv of the negative power supply and then decreases as the output transistors are driven further into saturation. the distortion performance of the amplifiers differs from conventional amplifiers. typically an amplifier? distortion performance degrades as the output voltage amplitude increases. used as a unity gain follower, the amplifier output will exhibit more distortion in the peak output voltage region around v cc 0.7 v. this unusual distortion characteristic is caused by the input stage architecture and is discussed in detail in the section covering input stage operation. output overdrive recovery output overdrive of an amplifier occurs when the amplifier attempts to drive the output voltage to a level outside its normal range. after the overdrive condition is removed, the amplifier must recover to normal operation in a reasonable amount of time. as shown in figure 41, the amplifier recovers within 100 ns from negative overdrive and within 80 ns from positive overdrive. v s = 2.5v v in = 2.5v r l = 1k to gnd in 50v r f r g r l t v out 100ns 1v r f = r g = 2k figure 41. overdrive recovery driving capacitive loads capacitive loads interact with an amplifier? output impedance to create an extra delay in the feedback path. this reduces circuit stability and can cause unwanted ringing and oscillation. a given value of capacitance causes much less ringing when the amplifier is used with a higher noise gain. the capacitive load drive of the amplifier can be increased by adding a low valued resistor in series with the capacitive load. introducing a series resistor tends to isolate the capacitive load from the feedback loop, thereby diminishing its influence. figure 42 shows the effect of a series resistor on capacitive drive for varying voltage gains. as the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less overshoot. adding a series resistor at lower closed-loop gains accomplishes the same effect. for large capacitive loads, the frequency response of the amplifier will be dominated by the roll-off of the series resistor and capacitive load. closed-loop gain ?v/v 0 capacitive load ?pf 10 100 1000 1 34 2 1 5 r f r g c l v out r s v s = 5 200mv step with 30% overshoot r s = 0 , 5 r s = 20 r s = 20v r s = 0 r s = 5 u figure 42. capacitive load drive vs. closed-loop gain
rev. a ad15700 ?1 high performance single-supply line driver even though the amplifier swings close to both rails, the amplifier has optimum distortion performance when the signal has a common- mode level halfway between the supplies and when there is about 500 mv of headroom to each rail. if low distortion is required in single-supply applications for signals that swing close to ground, an emitter follower circuit can be used at the amplifier output. v out v in 49.9 200 2.49 2.49 49.9 10 f 5v 0.1 f 49.9 2n3904 figure 43. low distortion line driver for single- supply ground referenced signals 2v 50mv 100 90 0% 10 1s 0.5v figure 44. output signal swing of low distortion line driver at 500 khz +9dbm vertical scale ?10db/div start 0hz stop 5mhz figure 45. thd of low distortion line driver at 500 khz figure 43 shows the amplifier configured as a single-supply gai n- of-two line driver. with the output driving a back terminated 50 w line, the overall gain from v in to v out is unity. in addition to minimizing reflections, the 50 w back termination resistor pro- tects the transistor from damage if the cable is short circuited. the emitter follower, which is inside the feedback loop, ensures that the output voltage from the amplifier stays about 700 mv above ground. using this circuit, very low distortion is attain- able even when the output signal swings to within 50 mv of ground. the circuit was tested at 500 khz and 2 mhz. figures 44 and 45 show the output signal swing and frequency spectrum at 500 khz. at this frequency, the output signal (at v out ), which has a peak-to-peak swing of 1.95 v (50 mv to 2 v), has a thd of ?8 db (sfdr = ?7 db). figures 46 and 47 show the output signal swing and frequency spectrum at 2 mhz. as expected, there is some degradation in signal quality at the higher frequency. when the output signal has a peak-to-peak swing of 1.45 v (swinging from 50 mv to 1.5 v), the thd is ?5 db (sfdr = ?0 db). this circuit could also be used to drive the analog input of a single-supply high speed adc whose input voltage range is referenced to ground (e.g., 0 v to 2 v or 0 v to 4 v). in this case, a back termination resistor is not necessary (assuming a short physical distance from transistor to adc), so the emitter of the external transistor would be connected directly to the adc input. the available output voltage swing of the circuit would, therefore, be doubled. 1.5v 50mv 100 90 0% 10 200ns 0.2v figure 46. output signal swing of low distortion line driver at 2 mhz vertical scale ?10db/div start 0hz stop 20mhz +7dbm figure 47. thd of low distortion line driver at 2 mhz
rev. a ?2 ad15700 ad15700 pinout (top view) common common common common common common common common common common common common common common common common common common a b c d e f g h j k l 12 34567 89101112 common common common 123456789101112 a b c d e f g h common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common common vref a gnd dac v out rpad1 rb1 ?n1 +vs1 cs_dac ra1 ?s1 ?s1 vout1 a gnd dac a gnd dac vdd dac + in1 rc1 sclk din dgnd dac cnvst rd d15 d14 reset + vs2 d13 d12 ?n2 ?s2 ref test1 busy d11 rderror d10 sync ?s2 + in2 rc2 common refgnd ina rpad2 rb2 ind avdd warp ser/ par d0 d2 divsclk0 d4 ext/ int a gnd adc ra2 inc byte swap ob/ 2c impulse d1 d3 divsclk1 d5 invsync v out2 inb pd cs_adc d6 invsclk d7 rdc/sdn ingnd a gnd adc a gnd adc ognd ovdd dvdd test0 a gnd adc dgnd adc d9 sclk d8 sdout m j k l m
rev. a ad15700 ?3 outline dimensions 144-lead chip scale ball grid array [cspbga] (bc-144) dimensions shown in millimeters seating plane 0.25 min detail a 0.55 0.50 0.45 ball diameter 0.12 max 1.70 max detail a 0.80 bsc 8.80 bsc a b c d e f g h j k l m 12 11 1 0 9 8 7 6 5 4 3 2 1 top view 10.00 bsc sq coplanarity a1 a1 corner index area compliant to jedec standards mo-205ac notes 1. the actual position of the ball population is within 0.15 of its ideal position relative to the package edges 2. the actual position of each ball is within 0.08 of its ideal position relative to the ball population 0.85 min
rev. a c03025??/03(a) printed in u.s.a. ?4 ad15700 revision history location page 2/03?ata sheet changed from rev. 0 to rev. a. edit to functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to amplifier electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 edit to adc pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 edit to figure 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 changes to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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